With increased frequency, data processing systems are employing a plurality of independent processors to perform individualized operations. This trend (multi-tasking) is due in part to the increased volume of data capable of being handled by modern semiconductor memory devices, and the desire to perform more than one task at a time.
While multi-tasking is known, there are major drawbacks associated with implementation. One such problem concerns the allocation of resources such as system memory.
When multiple processors are used in a single system, there must be control over when, and in what priority, the various processors will have access to memory. In response to this need, various prior art systems utilizing multiple processors dedicate an entire processor, aided by an advanced operating system, to manage all the allocations of a large main memory. Unfortunately, such a sophisticated operating system is simply not practical for smaller applications.
Another approach suggests that each processor be given an individual dedicated memory. While this presents a much simpler solution, rigidly dedicated memory creates an extremely inflexible data processing environment, the cost of which becomes prohibitive as more processors are added.
Another problem associated with the utilization of multiple processors is the speed at which the data processing system operates. This concern becomes more prominent as one employs processors that operate asynchronously to each other, an interface device, or to the memory units.
In conventional data processing environments, the speed of operation is governed by the slowest processor, herein after referred to as a memory access device. In order to achieve moderately efficient throughput, systems housing both fast and slow memory access devices could either physically separate these devices onto separate buses, partition system resources between the devices, or arrange the system to operate synchronously with the memory unit.
In other prior art systems, a large common memory is subdivided into various discrete pages. Each memory access device is dedicated a page. Within each page, a memory access device can address a plurality of subdivisions or blocks of memory. In this way each memory access device can address memory, yet remain confined to a separate and unique memory environment.
While this approach addresses the above-mentioned problems, it nevertheless demands the use of an extremely large memory unit. Thus, for systems not requiring massive amounts of memory, this solution borders upon the impractical.
Other prior art systems have adopted the single fast memory approach, wherein a plurality of asynchronous memory interface devices access one block of common memory (see FIG. 1). While devices within that plurality operate at various rates, only one can access memory at a time. Accordingly, the common block of memory must have a very fast access time; faster than the rate of operation of the fastest memory access device. By definition, access time is the time required by a memory device to store or retrieve data upon receipt of an address. Presently, fast memories are very expensive. When used in an environment dominated by slower rate transactions, system throughput and efficient economic management is minimized by the failure to utilize full memory capability.
It would, therefore, be extremely advantageous to provide a data processing system employing a plurality of smaller, less expensive memories having various access times. This processing system shall be controlled such that several memory access devices can address several memory units, without the necessity of a complex operating system, or the inflexibilities imposed by dedicated, fast, or large memory.